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ASuba
Novice
499 Views

Using DCFIFO from Quartus IP in Qsys with avalon mm at write side

Hi all

Hi Iam workign with Cyclone v FPGA.

I am using DCFIFO from Quartus IP mapped to avalon mm interface where write side of FIFO is connected to avalon mm and read side is to the custom IP in QSYS system. I need a condition such that once FIFO is full with continuose writes, the avalon mm should wait until the FIFO is read from custom IP side (ie FIFO wrfull is deasserted )such that data write happens after that. How can I acheive this ? How to manipulate Avalon mm bus writes ?

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7 Replies
AnandRaj_S_Intel
Employee
104 Views

Hi Athira,

 

Yes, you can do that using some logic in your custom component.

 

  1. Interface your DCFIFO and custom IP.
  2. Write a logic in custom IP to control DCFIFO read/write.

 

Refer below links design example and DCFIFO & avalon mm user guides.

 

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-ip.html

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/ug/ug_fifo.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

 

Regards

Anand

 

ASuba
Novice
104 Views

Hi Anand

 

I already did the steps you mentioned above. But I am not sure how to acheive the control of making avalon to wait until the FIFO is not full . What would be the procedure to do the same ?

AnandRaj_S_Intel
Employee
104 Views

​making avalon to wait until the FIFO is not full

 

>>Avalone is in wait state until you given write or read signal from custom component.

If fifo is full assert read signal & deassert write and when if fifo is empty assert write signal & deassert read.

 

 

ASuba
Novice
104 Views

Hi

 

Yes I need to write in to DCFIFO when its not empty and need avalon to wait if the FIFO is full so that atleast once data is read out and its filled at same time.

I am not sure how to get this avalon wait signals from qsys.

AnandRaj_S_Intel
Employee
104 Views

​Okay,

 

  1. You can write to fifo if empty/rdempty/wrempty asserted and full//rdfull/wrfull is deassert.
  2. Read from fifo if empty/rdempty/wrempty deassert and full//rdfull/wrfull is asserted.

Which will make avalone bus wait.

 

Regards

Anand

 

ASuba
Novice
104 Views

Hi Anand

I am doing the same. I am sending data continuosly using the Software in Linux.(HPS system). How can I qualify the wait while I send the data continuosly ?

AnandRaj_S_Intel
Employee
104 Views

A slave asserts wait request when unable to respond to a read or write request. Forces the master to wait until the interconnect is ready to proceed with the transfer. 

You have should have wait logic in slave design to control it.

 

Please open a new case for further Query.

 

Regards

Anand

 

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