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Valued Contributor III

Using HPS2FPGA from HPS point of view



I am a pure SW developper and not familiar with FPGA and how it works. I have to develop a soft working on the Cortex A9 in the Cyclone V SoC. Another team configures the SoC and develops the FPGA part. I 'd like to have an overview of how the HPS2FPGA works. (for now, forget the init part). 


Let suppose that we decide that the zone is divided in 32-bits unsigned dwords, that we call D1,D2,D3,etc.. 

Let say I want to read the datum Dn 

I do something like that (please, don't take into account C code quality) in my HPS/Cortex code : 

volatile uint32_t *p_base = (uint32_t*)0xC0000000; uint32_t const value = p_base; ... 


Here is how I understand the p_base[n] will execute: 

  • A9 Core request for reading the 32 bit word at adresse 0xC0000000 + 4*n  

  • L2 cache adress filtering detects it's an adress for the system interconnect  

  • L2 cache puts the AXI read request on the AXI bus with the L3 main switch  

  • The L3 main switch routes the request to the AXI bus with HPS-to-FPGA Bridge  

  • In the FPGA, the HPS-to-FPGA Bridge is "plugged" to an AXI slave implementation  

  • The FPGA AXI slave implementation receives the request and translates the adresse 0xC0000000 + 4*n into whatever it wants and builds and answer according to its implementation  

  • The FPGA AXI slave implementation sends the read respons to the L3 main switch through the AXI bus  

  • The L3 sends the AXI read respons to the L2 cache  

  • The L2 cache serves the data to the Cortex.  



Is it something like that ? 


Apart initialisation where I have to remap the HPS2FPGA zone (bit 3 of remap set to 1), I do not have to do anything else in the C code for accessing the HPS2FPGA part ? Adressing the zone between 0xC000 0000 and 0xFC00 0000 is enough for having something happening in the FPGA ? 

Thanks in advance for your help, 


[EDIT] : don't know if it matters but SW is baremetal in the Cortex (linux not used)
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