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ArthurDent
New Contributor I
1,358 Views

Using PHY with RMII interface on Cyclone V SoC

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Hi

I have added a second PHY to my board and connected it through the FPGA IO. I will use one of the HPS EMACs.

The PHY is a 100Mb device with a RMII interface (not RGMII). What is the recommended way of doing this? As far as I can see there are no IP available for this (only GMII - RGMII). Do I have to write my own RMII to MII converter for this, or am I missing something?

BR

AD 

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1 Solution
Deshi_Intel
Moderator
371 Views

Hi,

I checked HPS EMAC spec as per attachment.

RMII is not supported in Cyclone V SOC. Yup, you need to write your own adaptor design if you insist to use it on CV.

Alternatively, you can switch to Arria 10 SOC or Stratix 10 SOC that support RMII.

Thanks.

Regards,

dlim

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6 Replies
Deshi_Intel
Moderator
372 Views

Hi,

I checked HPS EMAC spec as per attachment.

RMII is not supported in Cyclone V SOC. Yup, you need to write your own adaptor design if you insist to use it on CV.

Alternatively, you can switch to Arria 10 SOC or Stratix 10 SOC that support RMII.

Thanks.

Regards,

dlim

View solution in original post

ArthurDent
New Contributor I
371 Views

Thank you for your reply.

Yes, it seems like I have to write my own adapter. Unfortunately Intel doesn't have an IP (like the GMII-to-RGMII Adapter) for RMII adaption, I guess most PHYs today are Gigabit devices.

Although it is not too complicated to write an MII-RMII adapter it is always some work related to the bit details, timing and tests, and there also has to be a communication link between the emac core and the adapter to switch between the 2.5M and 25M clock to support both 10Mb and 100Mb.

/AD

Deshi_Intel
Moderator
371 Views
posted a file.
JOHI
New Contributor II
371 Views

Hello,

 

There is FPGA IP that might do the job:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

Tutorials are also available.

 

1. About This IP Core

The Intel FPGA Triple-Speed Ethernet IP core is a configurable intellectual property

(IP) core that complies with the IEEE 802.3 standard.

It incorporates a 10/100/1000-Mbps Ethernet media access controller (MAC) and an

optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded PMA

built with either on-chip transceiver I/Os or LVDS I/Os. When offered in MAC-only

mode, the IP connects with an external PHY chip using MII, GMII, or RGMII interface.

The IP core was tested and successfully validated by the University of New Hampshire

(UNH) interoperability.

 

Best Regards,

Johi.

joaofl
Beginner
300 Views

Im in the very same situation. @ArthurDent, have you implemented it yourself in the end? Would it be possible to share the IP?

Thank you.

ArthurDent
New Contributor I
278 Views
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