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Valued Contributor III
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Using PLL_L_CLKOUT on a MAX10

Hello, 

 

I'm using multiple Max10 devices: 10M02SCU169I7G 

 

I would like to use the DIFFIO_RX_L19 to output the PLL CLK (negative = pin M3 and positive is L3).  

The pin optional functions are PLL_L_CLKOUT (n and p) so I assume it would work. 

 

This output is going directly to anothers MAX10 CLK2 diff input pair.  

 

But when i assign the outputs as differential LVDS, the compiler is giving me following error: 

Error (169175): Pin "CLK_OUT" with LVDS I/O standard needs a differential output buffer which is not available on location L3. 

 

Who can help me? 

 

With kind regards, 

Wouter
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Valued Contributor III
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Hi,  

 

Error means that there is no available true LVDS buffers on those pins. Use LVDS_E_3R I/O standart, by using this standart you have to use external board resitors.  

 

Regards,
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Valued Contributor III
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I though i read something about the differential part was only accessible true the ALT PLL or something but i can't find where i read this.  

Your solution will work but it needs a fix to all the proto boards.  

 

Thx
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Valued Contributor III
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Someone will correct me if I am wrong but those pins can work in differential mode (this does not mean LVDS) fitter simply routes your signal to 'p' pin directly and to 'n' trough NOT gate. This means that your output works in voltage mode and you need external resistors to suit LVDS standart. True LVDS output buffers works in current mode and you do not need to add external resistors at transmitter side. So in conclusion Quartus says that there is no such buffer that can be used to implement true LVDS buffer in those pins. If there is no such thing then you cannot acces it trough PLL or any logic. 

 

Please share if you will found any other solution.  

 

Regards
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Valued Contributor III
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DIFFIO_RX outputs don't support true LVDS drivers. You can either switch to LVDS_E_3R, as suggested, or use a DIFFIO_TX_RX pair. In the latter case you also get increased jitter and skew due to non-dedicated clock routing.

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