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Using RiscFree for Nios V Development: Error occurred attempting to halt the target during discovery

allenS1
Employee
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I am trying to run a Hello world program on the Nios V processor using an Agilex I-Series Transceiver SOC Dev Kit. The example that I'm trying to generate is found here in the Nios V Handbook, under the Quick Start guide section. This example design is supposed to be targeted for the Arria 10 Soc Dev Kit, but I'm trying to modify it so it works for the Agilex Dev kit that I have. To that end, I've changed the Device in the Platform Designer System that I created. I changed the Device ID in the create_qsys.tcl file that's included in the example project. I changed the Device in the Quartus Project. I selected a new clock pin that works for the Agilex board. I included the SmartVID settings for the Agilex board in the top.qsf file. And after I got the Quartus project to successfully compile, I made sure the programmer had the right device selected.

 

I was able to download the .sof file to the board with no issues, after which I followed this guide to create and build a project using RiscFree and download the program. Specifically, I followed Section 4 for Debug Setup. I was able to get to the point where I made all the proper debug configurations and click Debug to download the project, but instead of seeing anything printed to the console, I received this error message:

 

Error in GDB server launch sequence
GDB server terminated

Ashling GDB Server for RISC-V (ash-riscv-gdb-server).
v22.3.0, 01-Jul-2022, (c)Ashling Microsystems Ltd 2022.

Initializing connection ...
Checking for an active debug connection using the selected debug probe (SN: 16777217):
Internal error. Could not halt the target: timeout occurred
Error occurred attempting to halt the target during discovery.

 

allenS1_0-1659037859578.png

I should mention that I tried the example originally as it was intended with the Arria 10 board before this, and it worked correctly, so I think the issue has something to do with me being thorough enough in making sure the example design could target the new board. Where am I going wrong?

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JingyangTeh
Employee
1,599 Views

Hi allenS1


Sorry for the late response. 

Noted on your question in this case.

Please give me some time to look in to this.

I will get back to you as soon as possible.


Regards

Jingyang, Teh


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JingyangTeh
Employee
1,591 Views

Hi allenS1


What changes did you made to the tcl file?

Could you try adding the the changes of the device, device family and clock pin assignment to the top.qsf file?


Regards

Jingyang, Teh


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allenS1
Employee
1,578 Views

Hi Teh,

 

Sorry for not updating you sooner, but this issue has been solved. I think the issue was with the IPs in the system I used needing to be upgraded. Once I performed an IP upgrade on the necessary components and recompiled, everything was able to work fine with no errors. I had already changed the device, device family, and clock pin assignments before posting this issue. Thank you for responding though.

 

Best,

allenS1

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JingyangTeh
Employee
1,568 Views

Hi allenS1


Great to hear that it is working for you.

Did you get a prompt to upgrade the IP when you are compiling the example for A10?

Or it only prompted you to upgrade the IP only when you compile for Agilex?


Regards

Jingyang, Teh


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JingyangTeh
Employee
1,559 Views

Hi allenS1


Since there are no feedback for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, someone will be right with you.


If you happened to close this thread you might receive a survey.  If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


Regards

Jingyang, Teh


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