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Hey guys,
I am relatively new to FPGAs. I'm trying to use my FPGA to output a VGA signal. At first, my screen kept entering power save mode, but I realized my timings were incorrect (vsync, hsync, etc). I needed a 25MHZ clock for 640x480 resolution but my board is only equipped with a 50MHZ clock. I created a PLL to generate a 25MHZ clock. Now, I am receiving the error "Auto adjust in progress". Any ideas as to how I can fix this problem?Link Copied
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post some code - we'll have a look.
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TO_BE_DONE
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have you testbenched the code - does it conform to specs?
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We haven't used test benches. I think we are doing something wrong with the 'n_blank' and 'n_sync' signals.
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Well, a testbench would tell you that. It would make debugging much much easier.

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