I have a design where I need to write data from the HPS to some FPGA cores, which spits output to get sent back to the f2sdram0 data port of the HPS.
For simple debugging I simply have an Intel AXI Bridge in the fpga section where the slave is connected to the h2f AXI master, and the master is connected to the f2sdram0 AXI data slave. They all share a 100 MHz clock. When I write to the AXI bridge from the HPS I just end up getting a bus error between the AXI bridge master and the f2sdram0 slave. Before attempting to write this data I run the u-boot pre-loader and a script which supposedly enables the FPGA-HPS bridges and disables the firewalls. I'm able to access SDRAM from the HPS directly no problem.
Any advice on getting the f2sdram port working?
Firstly, I would want to make sure the bridges are enabled properly,
Bridge configuration for Stratix 10 can be found here: