I'm using Cyclone IVE device (EP4CE55F23). Here are my doubts:
(a) The VCCINT rail consumes 2.3A and VCCD_PLL rail consumes 42mA. I plan to supply both rails from a single power plane (without any ferrites) and limit the ac ripple to 15mV, giving a target impedance of about 13.25 milliohms. Is it okay to do so? What is the noise tolerance of VCCD_PLL rail?
(b) The VCCIO_2.5V rail consumes 125mA and VCCA rail consumes 47mA. I plan to supply both rails from a single power plane (without any ferrites) and limit the ac ripple to 15mV, giving a target impedance of about 123 milliohms. Is it okay to do so? What is the noise tolerance of VCCA rail?
(c) If I have to separate VCCIO_ 2.5V and VCCA, can I connect JTAG connector to VCCIO plane instead of VCCA plane?
Hi Binayak Shrestha
Referring to pin connection guideline of doc below:
For question (a) and (b), referring to page 8, example 2 for Cyclone IV E:
"May be able to share VCCD_PLL with VCCINT with a proper isolation filter. With proper isolation filter, limit the VCCD_PLL power supply to ±3% maximum ripple voltage. Depending on the regulator capabilities this supply may be shared with multiple Cyclone IV devices. Use the Early Power Estimation (EPE) tool within Quartus II to assist in determining the power required for your specific design."
"If VCCIO requires 2.5 V, may be able to share VCCA with a common 2.5 V supply with a proper isolation filter. However, for any other VCCIO voltage you will require a 2.5 V regulator for VCCA. Use the EPE tool to assist in determining the power required for your specific design."
For question (c), we can refer to page2 of the same doc for jtag pin connection.
Hi Eng Wei,
My main aim is to remove the isolation filters from VCCA and VCCD_PLL and still use the same power plane.
(a) With VCCINT = 1.2V, the noise maximum noise ripple allowed on VCCD_PLL = 3% of VCCINT = 36mV. If I maintain a 10mV ( much less than 36mV) noise ripple across the power plane, can't I power both VCCINT and VCCD_PLL with the same power plane without using any isolation filter?
(b) Maximum allowed noise ripple on VCCA = 3% of 2.5V = 75mV. If I maintain a 10mV ( much less than 75mV) noise ripple across the power plane, can't I power both VCCIO_2.5V and VCCA with the same power plane without using any isolation filter?
(c) What I have understood is that both VCCA and JTAG power pins need 2.5V. It doesn't matter if they are powered from the same source or a different source.
Sorry for late response as I was getting around with more spec and discussion before getting back to you.
For 1st and 2nd question, the recommendation from the spec is always guaranteed by certain level of implementation validation and characterization for jitter performance. If we would like to have different implementation from the spec, due to design limitation, then we can utilize tools like Power Distribution Network (PDN) Design tools for analysis.
Unfortunately I couldn't find any better power isolation filters guideline for Cyclone family at the moment, but below doc can be use as reference (Stratix IV) for power isolation filter usage and analysis.
For 3rd question regarding JTAG connection, yes, we can use any other 2.5V power supply as long it is supplying a stable 2.5V.
Here is the ref:
I am truly sorry for the late response, as I was a away for a while and overlook the response here after came back. You are right, the doc AN583 seems to be removed after I was able to read it the other day when I posted here. I am not able to retrieve it from internal database too. I do not find any replacement of this doc at the moment. I believe the doc is removed base on regular update in the database maintenance.
The published documents might get removed due to different reasons such as outdated, not supported and etc. If the apps note you found is not published by Intel, we might not able to support its usage, but definitely we can bring up any concern part for discussion.
It is published by Altera some years back. Now it is completely removed by Intel team. Mine is the following doubt - was the appnote wrong in engineering concept and hence was removed?
It is important to know the reason because it will bring clarity on whether we can use the old app note or not.
I will transition this case to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.