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Altera_Forum
Honored Contributor I
801 Views

VCXO removal in Stratix 10 E/H -tiles

Hi, 

 

I am currently investigating Stratix 10 transceiver capabilities. I have a need to create several Tx clocks that lock to a several recovered Rx clocks but I cannot have external VCXO:s to support this (the HW design is already completed). I have come across a brief description of this being done internally by a fPLL and sigma delta modulation in Stratix V devices. Is this possible for Stratix 10 E-tiles? 

 

I have not managed to find any description of this being done with a Stratix 10. I know it is possible in the Xilinx 7-series through to the Ultrascales as in this application note: https://www.xilinx.com/support/documentation/application_notes/xapp1276-vcxo.pdf 

 

 

/Jens
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Altera_Forum
Honored Contributor I
31 Views

I am answering this myself for anyone out there looking for the same thing: There is a possibility to do VCXO removal in H-tiles and only for SDI and OTN. E-Tiles do not support this.

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