Re: VHDL/Modelsim bug?

Altera_Forum · ‎10-14-2011

Hello, i have two modules sending signal to each other, one module has the following code

when WAIT_REQ_DATA =>
        -- Wait for a requisition from the Goertzel module
        if req_data = '1' then
          calibration_state_next <= ASK_DATA;
          get_data_reg_next      <= '1';
        else
          calibration_state_next <= WAIT_REQ_DATA;
        end if;

while the other has this code

when WAIT_ENABLE =>
          get_sample_next <= '0';
			 if  data_ready_i = '1' then 
			   state_core_next <= LOOP_PRINCIPAL_P1;
			        else
          state_core_next <= WAIT_ENABLE;
			 end if;

Everything seems ok and it works for 185 times... then it stops to work (when the data_ready_i goes to 1 my state doesnt change in the second module)

I made a change in my code to this:

when WAIT_ENABLE =>
			 if  data_ready_i = '1' then 
                                            get_sample_next <= '0';
			   state_core_next <= LOOP_PRINCIPAL_P1;
			        else
          state_core_next <= WAIT_ENABLE;
			 end if;

And then we can see in the screenshot that in the 185th time my module needs the data_ready to be one for two clock pulses

There is absolutely no sense on this... why would everything work for 185 times and then stop? I am in the right state working for the pulse and the pulse happens...

any help is welcome

Altera_Forum · ‎10-14-2011

how do you generate data_ready_in.

if it is not generated on same clock you might get problems of delta delay or actual delay that is not visible in waveforms

Altera_Forum · ‎10-14-2011

Both modules are recieving the same clock input (50 mhz) directly from the pin.

Data_ready_in is an input that is connected in the get_data_reg_next from my second module


when INCREMENT =>
        -- Increment signals for processing
        data_output_reg_next   <= acc_reg;
        data_ready_reg_next    <= '1';

and it goes to zero one state after..

Altera_Forum · ‎10-14-2011

It's like the IF isn't working, can't be more clear then IF IN = 1 change state

and the IF is going to one.. seriously

Altera_Forum · ‎10-14-2011

As such it is perplexing without knowing fullm picture. However I note the change occurs when get_sample gows low. Do you have any conditions apart from if somewhere up the process

Altera_Forum · ‎10-14-2011

Nope.

Well, i registed the input and everything works fine now but i shouldnt need to register the input..

Altera_Forum · ‎10-14-2011

how about posting the code and testbench?