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Altera_Forum
Honored Contributor I
870 Views

VHDL Port Mismatch Error

Hi Everyone,  

 

I have defined a component in my VHDL Flash file as shown in the Capture 1 attachment.  

 

And I have generated a Flash IP. 

The Flash is instantiated as shown in Capture 2.  

 

When I compile the code, it throws in an error saying:  

 

Error (12012): Port direction mismatch for entity "Flash_intf:Flash_Interface_Program|Flash:Flash_inst" at port "flash_nwe". Upper entity is expecting "Input" pin while lower entity is using "Output" pin. 

 

Can anyone please tell me why am I getting this port mismatch error? 

 

Thank you
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6 Replies
Altera_Forum
Honored Contributor I
133 Views

You don't show the upper-level (or top-level) ports, but usually write enable and the other control signals are outputs to a flash device, not inputs.

Altera_Forum
Honored Contributor I
133 Views

 

--- Quote Start ---  

You don't show the upper-level (or top-level) ports, but usually write enable and the other control signals are outputs to a flash device, not inputs. 

--- Quote End ---  

 

 

Thank you for your reply.  

But I am getting the same error for address as well. The Flash_address is input std_logic_vector of 23 bits.  

But it still says  

 

Error (12012): Port direction mismatch for entity "Flash_intf:Flash_Interface_Program|Flash:Flash_inst" at port "flash_addr". Upper entity is expecting "Input" pin while lower entity is using "Output" pin. 

 

I don't think address is also output.  

 

Can you suggest what might be going wrong with this parameter? 

 

Thank you once again.
Altera_Forum
Honored Contributor I
133 Views

Of course address is an output. That's how you choose an address location on the flash to read or write.  

 

Can you post your top-level ports?
Altera_Forum
Honored Contributor I
133 Views

Can you draw a block diagram of how you think everything is hooked up? It can helpmin understanding what is going on.

Altera_Forum
Honored Contributor I
133 Views

Thank you for replying. I was able to solve the problem. Thank you for your time.

Altera_Forum
Honored Contributor I
133 Views

Thank you for replying. I was able to solve the problem. Address has to be output like you said. Thank you for your time.

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