Dear Technical team,
Developed test program for switch IC using VHDL and simulated with modelsim software. Result is in the 'Z' state .
Kindly support me to solve this issue..
please find the below for VHDL model of switch IC ,
ENTITY EN_DG221 IS
lblEN : IN STD_LOGIC;
lblA1 : INOUT STD_LOGIC;
lblY1 : INOUT STD_LOGIC
ARCHITECTURE ARCH_EN_DG221 OF EN_DG221 IS
lblY1<= lblA1 when lblEN ='0' else 'Z';
IC Model development Team,
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Intel Customer Support Technician
It's not clear whether you're trying to create a tri-state output or a bidirectional I/O. Your ports are bidirectional, but your logic is for a tri-state output.
If it's supposed to be a tri-state, lblY1 should be an out, not inout.