VHDL simulation using modelsim software

[VHDL]

Dear Technical team,

Developed test program for switch IC using VHDL and simulated with modelsim software. Result is in the 'Z' state .

Kindly support me to solve this issue..

please find the below for VHDL model of switch IC ,

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY EN_DG221 IS
PORT (
lblEN : IN STD_LOGIC;
lblA1 : INOUT STD_LOGIC;
lblY1 : INOUT STD_LOGIC

);
END EN_DG221;
ARCHITECTURE ARCH_EN_DG221 OF EN_DG221 IS

BEGIN

lblY1<= lblA1 when lblEN ='0' else 'Z';

END;

--
Regards,

Kalidasan G,

IC Model development Team,

[David_G_Intel]

Hello VHDL

Thank you for posting on the Intel️® communities. We will move your question to the correct sub forum, for future FPGA requests please post under FPGAs and Programmable Solutions 

Regards, 

David G 

Intel Customer Support Technician

[sstrell]

It's not clear whether you're trying to create a tri-state output or a bidirectional I/O.  Your ports are bidirectional, but your logic is for a tri-state output.

If it's supposed to be a tri-state, lblY1 should be an out, not inout.