VHDL std_logic_vector Comparisons

[Altera_Forum]

What's the best way to compare std_logic_vector 's to zero in VHDL? I don't want to use conversion functions, create a std_logic_vector of "0"s, or do element-by-element comparisons.

[Altera_Forum]

My personal favourite is OR_REDUCE() from IEEE.STD_LOGIC_MISC (in quartus\libraries\vhdl\synopsys), although it's a non-standard, like STD_LOGIC_ARITH

[Altera_Forum]

Thanks FvM! I'm going to use AND_REDUCE() since the only way for a (unsigned) std_logic_vector to equal zero is if all its bits, and hence the ANDing of these bits, is '0'.

[Altera_Forum]

You can create a std_logic_vector of zeros using "others" that's nice. 

constant bus_width : integer := 32;   signal my_signal : std_logic_vector(bus_width -1 downto 0); constant zeros : std_logic_vector(bus_width -1 downto 0);   zeros <= (others => '0');   ... if (my_signal = zeros) then...   This makes it a little cleaner.

[Altera_Forum]

--- Quote Start ---  You can create a std_logic_vector of zeros using "others" that's nice. constant bus_width : integer := 32;   signal my_signal : std_logic_vector(bus_width -1 downto 0); constant zeros : std_logic_vector(bus_width -1 downto 0);   zeros <= (others => '0');   ... if (my_signal = zeros) then...   This makes it a little cleaner.  --- Quote End ---    You cannot "assign" a constant, you can only initilise it at declaration.   For the origional poster - Im on the opinion that its always best to write explicitly what you mean. So if you are checking that all bits in the bus are zero, then use the and_reduce, or when VHDL 2008 gets support, you can just write the following:  if (and my_slv) then ....  But if your std_logic_vector represents a number, compare it to the integer 0.  if my_slv = std_logic_vector( to_unsigned(0, my_slv'length) ) then ...  Now I know you said you didnt want to have type conversion functions, but this way shows to another engineer that your std_logic_vector represents an integer and not just a collection of bits. This would beg another question though - why are you using std_logic_vectors to represent integers?

[Altera_Forum]

--- Quote Start ---  I'm going to use AND_REDUCE()  --- Quote End ---  Yes, that's better.  P.S.: I understood "What's the best way" is asking for a convenient way without writing too much text. VHDL is verbose enough anyway. For this simple reason, the original poster did not want to define compare strings and similar stuff. The compiler will convert any equivalent expression to anding all bits.  P.P.S.: I completely agree with Tricky, that numeric quantities should use numeric types and also numeric constants.

[Altera_Forum]

FvM did best understand and respond to my original post. 

 But Tricky brought up a good point. My std_logic_vector does represent an integer. An integer that represents a calculated distance from a sensor. I set this integer to zero when the distance is not in a valid range for my application. That way I only need 1 "done" signal to accompany the "distance" integer to know when the distance is ready to be read. I don't need an additional "valid" signal to indicate that the distance is in my valid range, since it will be zero if it's not.  I haven't coded in VHDL for a couple of years. Can integers be synthesizable entity ports? I have my "distance" as a std_logic_vector instead of an integer cuz I need to pass it b/t entities.

[Altera_Forum]

Sure - you can even have record types on the entity. 

 One problem with integers could mask initialization problems when comparing gate-level simulations with RTL: there is no "X" value for integers. So I try to stick to slv.

[Altera_Forum]

--- Quote Start ---  Sure - you can even have record types on the entity.   One problem with integers could mask initialization problems when comparing gate-level simulations with RTL: there is no "X" value for integers. So I try to stick to slv.  --- Quote End ---    True, but if you are not too concerned with gate level simulation, there is no worry.  Use any type you want for any ports, but at the top level, use a bit-array type, or record of bit array types so you can map each bit to individual pins.