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Altera_Forum
Honored Contributor I
1,789 Views

VHDL to schematic

hi 

hope if any one knows how to convert VHDL codes to schematic drawing, can this be done by altera software, or there is different software should be used 

thank you so much
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7 Replies
Altera_Forum
Honored Contributor I
375 Views

After synthesis, go to Tools -> RTL Viewer. It's by no means perfect(you're not going to print out nice clean schematics) but it's useful for understanding how the VHDL was interpreted. Why do you want the schematic? Documentation purposes? So you can edit it? To try and visualize the RTL? Something else?

Altera_Forum
Honored Contributor I
375 Views

thnak you for the reply, i am using max plus 2 , do you think , i will be able to do it, i am doing it just for some resaon to compare between the schematic and Vhdl codes program,,,

Altera_Forum
Honored Contributor I
375 Views

I'm pretty sure Max+Plus 2 doesn't have that. Download the web edition of Quartus. I think it has that, but to be honest, am not 100% sure.

Altera_Forum
Honored Contributor I
375 Views

thank you once again for the reply, it is highly apprecaited, i will try to down load Quartus web edition and see if it works,,, 

just have another question about a program i alreday wrote in VHDL , when i simulated the program , in the wave form , i can not see the names of my states, the wave is correct but instaed of writing the names of the states it deals with them like numbers 0,1, 2, 3, 4, 5, 6, 7, i will be so thankful to you for the help
Altera_Forum
Honored Contributor I
375 Views

what did you simulate with? 

If it was a post synthesis simulation, it will have encoded your states into binary.
Altera_Forum
Honored Contributor I
375 Views

thank u for the reply, i downloaded the Quartus web edition, it does not support RTL as it is limited software, i am trying to write a code for T-bird ford tail lights, i did write the program , have you ever coem across such a program

NChan38
Beginner
375 Views

You can now automatically generate a great schematic block view from verilog/VHDL/SystemVerilog with RTLVision PRO or StarVision PRO https://www.youtube.com/watch?v=_8Vub7mVhSI

 

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