I'm working on an application for a high EMI environment and need to constantly verify the configuration of an FPGA to ensure that the circuit isn't being damaged/altered by the noise. I know I can do it prior to programming the device, but how do I go about reading/verifying the configuration of a chip that's already been programmed? Is there a way to access the LUTs from the JTAG header? I don't need to know where the problem occurs, only whether something's been altered. A go/no go scenario, where any change causes me to halt the chip. If not JTAG, is there any other way for me to accomplish this?
That looks like it could work. I'm also investigating CPLDs for this use case, is there anything similar for those? I see that the MAX10 family can use the SEU IP but I don't see anything about the MAX V family. Ideally I'd like to be able to do a real-time checksum on the program memory and verify that it's still good.