Verilog Compiliation Error

Altera_Forum · ‎08-21-2009

Hi,

I am trying to implement a scaling function for the FFT Megacore Function. I copied and modified the Verlilog code from http://www.altera.com/literature/an/an404.pdf. My modified code is attached. However, Quartus doesn't compile, claiming a syntax error, which I have also attached.

Someone pls tell me where i have gone wrong. I am totally new to Verilog and have no idea what is wrong. Thanks.

Altera_Forum · ‎08-21-2009

A case statement can only exist inside an always block.

always @* begin
     case(exp_0)
     ...
     ...
     endcase
end

Altera_Forum · ‎08-21-2009

oh ok, i didn't know that. thanks jakobjones!! i'll go try it out now.

Altera_Forum · ‎08-24-2009

I have modified the code and added in a couple of lines but now, the error is that the "Top partition does not contain any logic". Attached is the new code. Anyone can help me on this? Thanks.

Altera_Forum · ‎08-24-2009

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I have modified the code and added in a couple of lines but now, the error is that the "Top partition does not contain any logic". Attached is the new code. Anyone can help me on this? Thanks.

--- Quote End ---

Hi,

I tried your source code in Quartus project (Quartus 9.0 SP2) and it finished sucessfully.

What was your toplevel when you run your project. BTW your are not using the clk, so get a lot of latches in your design. Is the code generated by the Megawizard ?

Kind regards

GPK

Altera_Forum · ‎08-24-2009

Hi,

I am also using Quartus 9.0 SP2 but it still comes up as "Can't synthesize current design -- Top partition does not contain any logic".

How do I find out my toplevel? Sorry, i'm pretty new to this stuff. No, not all the code was generated by Megawizard, only the inputs and outputs. The rest are from a website provided by Altera (http://www.altera.com/literature/an/an404.pdf) (http://www.altera.com/literature/an/an404.pdf)

Thanks for your response.

Altera_Forum · ‎08-24-2009

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Hi,

I am also using Quartus 9.0 SP2 but it still comes up as "Can't synthesize current design -- Top partition does not contain any logic".

How do I find out my toplevel? Sorry, i'm pretty new to this stuff. No, not all the code was generated by Megawizard, only the inputs and outputs. The rest are from a website provided by Altera (http://www.altera.com/literature/an/an404.pdf) (http://www.altera.com/literature/an/an404.pdf)

Thanks for your response.

--- Quote End ---

Hi.

why do you generate only the ports with the Megawizard? I think the code in the application note is only an example to show how it works.

Can you post your Quartus project as a tar-file in the forum ?

Kind regards

GPK

Altera_Forum · ‎08-24-2009

Apologies, I didn't use Megawizard at all. I just used a block tool and created a design file from the block. There's nothing else on the board except that function. As you adviced, I have included the function to work on the positive clock edge.

yeah, i know the code given is only an example, but that's exactly what i'm trying to do. just a simple scaling function. Didn't think i'd run into this much problems...:(

Altera_Forum · ‎08-24-2009

--- Quote Start ---

Apologies, I didn't use Megawizard at all. I just used a block tool and created a design file from the block. There's nothing else on the board except that function. As you adviced, I have included the function to work on the positive clock edge.

yeah, i know the code given is only an example, but that's exactly what i'm trying to do. just a simple scaling function. Didn't think i'd run into this much problems...:(

--- Quote End ---

Hi ,

can you post the file "test_scaling", where you use the scaling block as an instance ?

Kind regards

GPK