Verilog HDL coding of "Clock divider by 3"

[Altera_Forum]

Hi. I'm "720_com" of Altera beginner. 

I want to create about verilog HDL coding of Clock divider by 3.   I make Clock divider by 3 Input Frequency : 75MHz Output Frequency : 25MHz   --------- module divide3_check(reset_n, clkin, clkout, ng);   input reset_n; input clkin; output clkout; output ng;   reg[1:0] counter_pos = 2'd0; reg[1:0] counter_neg = 2'd0;   always @(posedge clkin or negedge reset_n) begin  if (~reset_n)  counter_pos <= 2'd1;  else if (counter_pos==2'd3)  counter_pos <= 2'd1;  else   counter_pos <= counter_pos + 2'd1; end   always @(negedge clkin or negedge reset_n) begin  if (~reset_n)   counter_neg <= 2'd1;  else if (counter_neg==2'd3)  counter_neg <= 2'd1;  else   counter_neg <= counter_neg + 2'd1; end   assign clkout = ((counter_pos != 2'd3) && (counter_neg != 2'd3));   reg[1:0] counter_neg_reg = 2'd0; always @(posedge clkin or negedge reset_n) begin  if (~reset_n)  counter_neg_reg <= 2'd1;  else if (counter_pos==2'd3)   counter_neg_reg <= counter_neg;  else   counter_neg_reg <= counter_neg_reg; end   reg ng = 1'd0; always @(posedge clkin or negedge reset_n) begin  if (~reset_n)  ng <= 1'd0;  else if (counter_pos==2'd3)  ng <= (counter_neg_reg != counter_neg);  else   ng <= 1'd0; end   endmodule   ---------   Please show you "rtlsim.png" and "gatesim.png". rtlsim.png -> RTL Simulation gatesim.png -> Gate level simulation   The both simulation result "clkout : 25MHz". But, Internal signal waveform is difficult.     Please tell me if there is a mistake in my description.   Best Regards,

[Altera_Forum]

The problem here is that you are using counters to create logic. it is going to give terrible results (bad results made even worse by the fact your output is the output of logic, not a register). 

 You should create a clock enable using a single clock. Then everything is on the same clock domain and you wont have any problems related to timing, temperature, voltage and process that you will have with your current implementation.