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Vhdl Alu

Altera_Forum
Honored Contributor II
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It is possible to create an ALU that add, subtracts and multiplies all in one? I cannot seem to get the multiplication to work because I need double the storage because the numbers are being multiplied. Do I just need to use different storage variables? Is there a "cleaner" way? 

 

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY ALU IS port(x, y : in std_logic_vector(7 downto 0); --variables on which opeation is performed operation : in std_logic_vector(2 downto 0); --how to choose what operation zero : out std_logic; result : out std_logic_vector(7 downto 0)); END ALU; architecture ALU_ARCH of ALU is begin process(operation) variable temp: std_logic_vector(7 downto 0); begin case operation is when "101" => temp := x + y; when "110" => temp := x - y; when "111" => temp:=x*y; when others => temp := x - y; end case; result <= temp; end process; end ALU_ARCH;
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Altera_Forum
Honored Contributor II
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Make result and temp 16 bit wide. Your ALU is not working properly in case of carries already, anyway.

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Altera_Forum
Honored Contributor II
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what do you mean by "carriers"?

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Altera_Forum
Honored Contributor II
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Hi, 

if you sum a number of 8 bits with another number of 8 bits the result may have 9 bits but your variable "temp" has only 8 bits! 

Eg: 1111 1111 + 1111 1111 = 1 1111 1110 

 

I think he said this!
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