I have a technical question regarding of "pcie avmm -> ddr4" logic path in "QSYS Interconnection".
When checking customer's PCIE AVMM Design for A10, I find their "PCIE -> DDR4" data path follows as below picture :
This is a PCIe gen3x8 AVMM example case in A10SOC. my personal understanding is :
- the "PCIE Hard IP core 's -> dma_rd(wr)_master" can connect to " emif_ddr4 's slave". that can satisfy the design.
WHY in customer's design, they insert two adstional Brdiges between PCIE Hard Code IP aand the EMIF DDR4 IP ?
the inserted two bridge are in picture :
" pipe_stage_ddr4a_dimm " ?
I just wonder why they exist in here ? ANyone has explanation ?
You are correct. In most cases, you don't need to manually add bridges to a design like this. Clock crossing logic is added automatically to the interconnect when the system is generated. However, you may want to add a bridge manually like this for more control over how the clock crossing is implemented. As for the pipeline bridge, that is used to adjust the topology of a system (for example, aggregate multiple exported interfaces into one) or add pipeline stages to improve performance.
So the short answer is that these bridges are optional.
Thanks @sstrell for detailed clarification.
Regarding of "Quartus Automatic Adding the internal bridge" vs "Customer defines the defined bridge", how could we compare and evaluate their performance difference, to decide which one to be used ? Do you have any idea ?
Thanks a lot
From performance perspective, usually without the bridge is the best because the latency is decrease. The bridge is add for some other purpose like both master-slave clock use different clock domain, multiple master to single slave or vice versa. You may refer to the description of the bridge as explain in this document, all bridge added is for some purpose.
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