We have a system where some lanes of an 8-lane receive-only 2.3 Gbps interface first become more susceptible to poor signal integrity (smaller eye opening) and eventually don't lock under any signal condition. Replacing the FPGA fixes the issue. We think that it's possibly caused by ESD but don't have an obvious source of ESD to point to. What else might cause this failure mode in the Rx PHY?
As I understand it, you have some inquiries realted to the potential degradation of the CVGX RX. For your information, if the device is operating under the condition following the datasheet specs ie power supplies, signal voltages and etc, I am not aware of degradation of CVGX XCVR. I think you might need to further look into potential ESD or other on-board condition ie power supplies stability which might lead to the device damage.
Please let me know if there is any concern. Thank you.