What is Cyclone IV JTAG threshold specification and where is it fully documented ?

[RH0001]

As far as I read it this is completely unclear in the data sheet, It states the inputs are schmitt and the hysteresis is 200mV for Vccio=3.3V BUT it fails to mention what the resulting VIL/VIH thresholds actually are! Does anybody know ?

As I am trying to debug the usual byte-blaster/FPGA non communication problem it would be useful to know. Vccio for all banks is 3.3V & byte blaster pin 4 is Vcca (2.5V) whilst the driving device is a 74HC244.

[YuanLi_S_Intel]

Hi R H,

For VIH and VIL of VCCIO 3.3V, you may refer to link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-53001.pdf (Page 12)

Thank You.

[RH0001]

Thank you for your reply, that is the point of the question, that document DOES NOT specify VIH & VIL for the schmitt input!

On page 12 it says there will be 200mV of hysteresis at 3.3V but FAILS to specify the resulting VIH & VIL.

So perhaps someone could answer the question please ?