What is Intel's recommended Exposed Pad size for Cyclone 10 LP FPGA EQFP package 144 Pin ?

[TDesk1]

I need to know the recommended Pad size for Cyclone 10 LP FPGA EQFP package, 144 Pin.

I have studied this document:

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04R00221-03.pdf

But there is not recommended Pad size for the Exposed Pad (Pin 145).

What is Intel's recommended Pad size for the Exposed Pad in EQFP144 Footprints ?

Is there available a PCBLib file for Altium that contains Intel's official Footprint for EQFP144 package ?

Thanks,

Christian

[NurAiman_M_Intel]

Hi Christian,

Thank you for contacting Intel community.

If you are referring to the pad size of pin 144, in the link you have given, "D2 and E2" are the exposed pad size.

If not, please explain which of the pad size are you referring to?

Sorry to let you know that Intel FPGA do not provide support for PCB footprint symbols for FPGA and CPLD device families, similar to configuration devices.

However, we will continue the support by providing the schematic symbol which you can download from the link above. You could have the schematic symbol in .olb format from the link below:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/pcb/pcb-cadence.html

Regards,

Aim

[TDesk1]

Hello @Aiman.N_Intel​ 

i am not asking about dimensions indicated in the documentation, which i know already, but about your recommended effective dimension for the Pad on the PCB.

We need to reduce any kind of possible issue related to soldering.

I need Intel's suggestion about how much make the Pad bigger or smaller with respect of the nominal size indicated in the datasheet and even considering any tolerance needed.

Can you please let me know suggestions, indications about how to properly size the PCB pad to eliminate or reduce as much as possible any kind of issue related to reflow soldering.

I hope now the request is more clear.

For example we are worried about how avoiding the risk that solder paste remains floating under the component and not soldered properly on the exposed pad which is not a visible problem with optical inspection (X-Ray inspection would be mandatory).

Not all manufacturers we work with can do x-ray inspection and therefore we would like to find a solution to avoid x-ray inspection still with guarantee of correct soldering of the FPGA component.

Thank you very much hoping in your reply soon,

Best Regards

Christian

[NurAiman_M_Intel]

Hi Christian,

Thanks for the clarification.

I will send you the image that contain dimension for the exposed pad in private message.

Regards,

Aim

[NurAiman_M_Intel]

Hi,

I believe my previous answer has address your queries. I will continue to close this case and feel free to open a new case if you have further inquiries.

Thank you.

Regards,

Aiman