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Altera_Forum
Honored Contributor I
1,537 Views

What is the best HDL language for the future: VHDL, Verilog or System Verilog?

Hello, which language is the best to learn for the future of FPGA design Verilog, VHDL or System Verilog? Or, is there something else that will replace the current languages? 

 

thanks, 

joe
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Altera_Forum
Honored Contributor I
114 Views

IMO, the best language to learn is the one that's most in use in the location you intend to live. For me this is Verilog. For my buddies on the east coast, it's often VHDL. SystemVerilog is to Verilog as C++ is to C -> Both will always be in use as the projects determines. 

 

That being said, Verilog is dead easy to learn...
Altera_Forum
Honored Contributor I
114 Views

From what Ive seen, VHDL tended to be used more by FPGA guys, with verilog used for both ASIC and FPGA. System verilog is only really useful as a verification language at the moment. But VHDL is getting a lot of features that make it match the power of System Verilog for verification, and theres seems to be a big push to get more people to use VHDL.

Altera_Forum
Honored Contributor I
114 Views

I typically code in VHDL due mainly to the fact that when I had to make the language selection, Altera MAX+Plus II's Verilog support was lacking a feature I needed. 

 

If put in the same position again, I would note that all of Altera's recent IP cores are being written in SystemVerilog (or perhaps Verilog). 

 

Mentor Graphics "Verification Academy" 

 

https://verificationacademy.com/ 

 

has a whole lot of resources on learning the correct way to code in SystemVerilog, and there's a couple of decent books on the subject 

 

SystemVerilog for Verification, Spear 

SystemVerilog for Design, Sutherland et al. 

 

You can also download the SystemVerilog specification for free. 

 

http://standards.ieee.org/getieee/1800/download/1800-2012.pdf 

 

So, although I'm still stuck in my ways and will continue to code in VHDL, I do see the advantage in learning SystemVerilog, and coding in whatever is appropriate for the particular task. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
114 Views

I‘m a beginner of the verilog, but i feel that it is easy.

Altera_Forum
Honored Contributor I
114 Views

VHDL is the devil's language. Most of commercial industry and west coast military firms use Verilog. Only the old dinosaurs military companies on the east coast use VHDL. It's about a 50% reduction in typing when using Verilog verse VHDL. Even now you are starting to see east coast military firms finally break down and adopt Verilog. Have you ever heard of System VHDL, no? VHDL will eventually go by the wayside like the software language Ada.

Altera_Forum
Honored Contributor I
114 Views

 

--- Quote Start ---  

Have you ever heard of System VHDL, no?  

--- Quote End ---  

 

 

Well, no, because VHDL already had a lot of the features SV brought to verilog. 

But I agree VHDL will become more sidelined. It will never go away completly, due to the large amount of legacy VHDL lying around, that will undoubtedly get re-used. Quartus still supports AHDL after all (and if you ever check the db directory, it's full of AHDL). 

 

But its not really the language thats important, its the technology. Theres a big push for C to gates technology now (again). And its actually much better than it was the last time around.
Shiv_Kumar
Beginner
114 Views

Verilog is a subset of System Verilog. The distinction is mostly that the subset which is understood by synthesis tools is mostly (old style) Verilog since SystemVerilog was mostly extensions to Verilog at the test-bench level (and the synthesis tools are usually old). I.e. you won’t get a different simulator/language, you’ll just be dealing with a different subset of SystemVerilog.

What industry needs (for DUT level design & test) is something that actually handles more abstractions and understands power properly. Verilog-AMS (which is a different standard) actually does a lot of the power stuff, but the SV guys hate all things analog and have not integrated it (and have no real plan to do so).

What the test-bench guys need is actually better C++ support so you can reuse your tests in production environments (after your chip is fabbed). The SV guys don’t like that either since it would be free.

The future will probably be asynchronous design methodologies done with C++, but in the meantime verification with SystemVerilog is in demand.

 

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