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What is the criteria that must be met for the "locked" output in the ALTPLL megafunction to go low?

CFisc1
Beginner
1,080 Views

I am using the ALTPLL IP block with a 30MHz reference clock and Quartus15.1.

 

From my understanding, the "locked" output of the ALTPLL megafunction will go low as soon as the phase frequency detector of the PLL detects a phase shift between the input reference clock and the feedback clock of the PLL.

 

There are given a number of reasons why this could happen in the MAX10 Clocking and PLL User Guide:

  • Jitter on the reference clock
  • Reference clock is not within the defined frequency
  • Noise on the power supply
  • etc.

 

Now my questions are:

  1. Is it true, that the only reason for the "locked" output to go low is the detection of a phase shift between reference clock and PLL feedback (whatever the reason for that may be)?
  2. If so, then how big does that phase-shift need to be in order to force the "locked" output low?

 

I am using the MAX10: 10M25SCE144 

 

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3 Replies
Rahul_S_Intel1
Employee
128 Views
CFisc1
Beginner
128 Views

Thank you for the response,

as I mentioned, I found the list of reasons which may cause the PLL to lose lock. What I do not know, and what I fail to find on the link you referenced, is: How are these "lock loss reasons" evaluated? My understanding so far is, that the only detection for any of the issues listed (Jitter, SSN, PLL reset) , is the detection of a phase difference between reference clock and PLL feedback loop. Is this assumption correct, or are there other means by which the PLL can detect a violation of the PLL specifications?

Thank you and kind regards

CFisc1
Beginner
128 Views

I am writing again, to ask about the status of my question.

If my question is not understandable, please tell me so. I can try to rephrase it to make it more clear.

Thank you

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