Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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What is the maximum clock speed, the maximum PLL speed, the maximum logic block input frequency and the minimum propagation delay through gates on the Cyclone 10 LP and GX FPGAs?

DMerc4
Beginner
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The more answers to the above questions I can get the better. Many thanks.

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Rahul_S_Intel1
Employee
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