What's state of I/O pins in Cyclone V GX FPGA, during POR, Configuration, & Initialization state ?

[kgupt8]

In 2011 documentation i found it as tri state during POR and Configuration. But in Latest Documentation , there is flowchart that shows all I/O pins are weak Pull Up. PLease clarify the value of all I/O pins during the 3 states of POR,Config and Initialization?

[YuanLi_S_Intel]

Hi Kapil,

Weak Pull Up means that the I/O is in tri-state. Thus, all I/O pin are in tri-state during POR, Configuration.

Regards,

YL

[kgupt8]

Thanks for clarifying. Can you please tell, After Configuration and till all Registers are initialized, do I/O pins remain in tri-state? ie the the first value output on I/O line is the initialized value after an I/O leaves tri-state? is that understanding correct?. having issues on board regarding power sequence implementation in cyclone V FPGA.

[YuanLi_S_Intel]

Hi Kapil,

Yes, unused IO will remain tri-state. May i know what is the problem with power sequence?

Regards,

YL