What's the internal tS and tH value of the resister inside FPGA?

[MinzhiWang]

Hello Guys,

We have one application to detect pulse or its rising edge. So two FFs are used to implement this function. The function diagram as following. We have to know the register's tS and tH parameters, because our input pulse width may be very narrow, for example, 1000ps. Does this structure garantee to capture so narrow pulse?

Another question is if the tS and tH can vary in different FPGA generations? Are the values same between Cyclone II and Cycone 10?

Pulse detection

[sstrell]

1000 ps = 1 ns which should be fine.  What's the clock frequency?  Yes, setup and hold times can vary.  The most accurate info would be from the timing analyzer in Quartus, though you would need to create a design (could be as simple as this diagram) and run an analysis.  There is a datasheet report in the tool (I forget the command) that would include setup and hold time info.

[TingJiangT_Intel]

I think your main problem is what's the max frequency your design can run at. You can use Timing Analyzer, click the "Report Fmax Summary", and refer to this report.

Also you can check the device datasheet to see the clock tree performance, like cyclone 10: