When will 0xdeadbeef be returned?

Altera_Forum · ‎04-28-2011

Hi folks:

I'm a device driver writer trying to get an FPGA working under Win7. (Porting from WinCE.) The device uses an Altera IP block to implement a generic PCI 2.0 interface to the HW/SW.

The bios/OS detect the fpga correctly and map the physical address (0xdff80000) correctly. (It would appear.)

This device wants to use memory mapped io to access the hw registers. When any access to the registers is performed the HW returns with 0xdeadbeef. (Using either the mapped virtual address or the physical address via a debugger produces the same result.)

I am assuming the Altera PCI IP core probably uses 0xdeadbeef as a default value to indicate it isn't happy with something.

So if anyone can give me some hints as to what might be wrong I'd be very happy. :)

Regards,

Brian

Altera_Forum · ‎04-29-2011

Got hold of the client verilog files...

Problem isn't in the Altera IP it's in the client decode of the register selects. :)

So... NVM...