Hi all,I thought there will be a PWM core/ip in Quartus Lite 15.1 (Qsys) but I think I'm wrong. Unless it has a weird name that I can't figure out. Is there one? Thanks
That took all of 5 minutes to write... - it would have been faster for you to have just written some HDL to do the job than the time you spent searching Quartus for such a simply design and then write this question and wait for answer.
module pwmGenerator# (
parameter CTR_WIDTH = 10 //Width of PWM counter
input tick, //Clock enable - to divide clock frequency as needed
output reg pwmOut
localparam ZERO = 0;
localparam ONE = 1;
always @ (posedge clock or posedge reset) begin
if (reset) begin
pwmCntr <= ZERO;
end else if (tick) begin
pwmCntr <= pwmCntr + ONE;
always @ (posedge clock) begin
pwmOut <= (pwmCntr < duty);
A Verilog implementation of the PWM was already provided on this forum, with the advantage to have the interface that allow you can build your own customized SOPC module to add it on Qsys such as you would do with a standard module, see that:re: sopc pwm module (http://www.alteraforum.com/forum/showthread.php?t=6492&p=26669#post26669)
I have a Question about PWM Core.
I understand i can make the PWM working with the above code but how can i control it with the NIOS software and how can i merge it with other interfaces like i want to use all I2C, SPI and interrupts.
Please reply thank you..