Which of VHDL or Verilog lets me build a two dimensional array with variable lengths of rows?

[KSimo1]

One of the main things my hardware sorting machine is going to have to do is compare two keys, each k bits wide. To do that I need a two dimensional array of signals, with ciel( log_2( k)) rows, and with variable lengths for the rows. Can such an array be constructed in VHDL? Can it be constructed in Verilog?

[ak6dn]

Are the lengths of each row static, or dynamically variable?

A 2D array is just that, a fixed array of rows of fixed size columns.

If the number of rows is static, but each is a different, fixed length, then you could define a structure. System verilog could handle this construct.

Otherwise, you need to just build a large 1D array of data, and a separate array of pointers/lengths into that array to manage the variable sized/positioned 2D elements.

Then you need to have some process (software or a complex state machine) that sets up all the pointers/lengths to manage your dynamically allocated/sized 2D array.

Note with any of these approaches you are going to get serial one word at a time access into your data structure, because it is just a big memory array of elements.

If you need simultaneous parallel access to data you have to build it with arrays of registers.