Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19098 Discussions

Why do Arria 10 GX transceivers lose disparity beat during data windows?

Honored Contributor II

I am using an Arria 10 GX, transciever in 8b10b mode to deliver a specific protocol (Arinc 818) over a fiber channel link. I can deliver my packets just fine, the link is great and solid, everything works except for one thing, running disparity (RD). 


Arinc 818 calls for all ordered sets to begin with negative running disparity -so say a 32 bit Idle Ordered Set (using a 32 bit interface), BC95B5B5 should come out on fiber with the 'BC' as the negative RD, the '95' as positive RD, and the 'B5''B5' both as neutral (because there is no negative/positive for that subset). 


I can force RD to be negative the way the Arinc818 spec calls for and the running diparity of all sets afterward toggle polarity as expected - that is until during data packets, the running disparity gets lost or indeterminate. So when the Control words come back the disparity for my 32 bit ordered sets begin positive. Using my example above, the 'BC' is now positive, the '95' is negative and the 'B5'B5' still neutral.  


Does anyone know how to hold the desired running disparity through data bursts? I am only doing a single force early after power up. In previous architectures, once you forced the disparity the way you want, it would stick forever. But in this new architecture, Data words throw it off. 


0 Kudos
0 Replies