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Why do I choose to allow retiming register, the data output will be wrong,for stratix 10 device.

michael16
Beginner
387 Views

Hi,

Here is the device I use:1SG280LN2F43I2LG
There are several phenomena:

1. if I choose the option of allow retiming register, the data output will be wrong or no data ,with good timing closure.  however, I don't choose the option, data output is right ,with bad timing closure.

2. I use the dont_retime attributes for part of modules , the result may be right or wrong at different frequencies .

I need your help with my problem , thank you.

retime.png

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9 Replies
sstrell
Honored Contributor III
365 Views

If you're meeting timing, but not getting the outputs you expect, then chances are your design code is not doing what you intend.  Perform a functional simulation or use a hardware debug tool like Signal Tap to verify the design in hardware.

michael16
Beginner
355 Views

Thanks your answer !

The output of functional simulation is meetting my expect, but my understanding is that retiming the register will not change the logic,Isn't it? 

sstrell
Honored Contributor III
353 Views

No, register retiming does not change logic function.  You are using a Stratix 10 device, so make sure you have hyper-retiming enabled.  That will work better with a Hyperflex device than the standard register retiming.

michael16
Beginner
350 Views

I did not find the option of hyper-retiming in Quartus 20.4.

Can this show that it has been turned on ? the screenshot below.

hyper.png

Nurina
Employee
320 Views

That's not the right setting. Go to Assignments->Settings->Compiler Settings->Register Optimization and make sure "Allow Register Retiming" is checked.


Regards,

Nurina


michael16
Beginner
306 Views

Hi Nurina,

Thanks for your answer.

You should scan the record above,  my problem is that as long as this setting is turned on, the data output is wrong .And I have tested my code in xilinx vu9p with no wrong .Because this project is big, so hardware debugging will take me a lot of time. 

Can your team help give some suggestions?tks. 

 

Best regards,

Michael

Nurina
Employee
285 Views

Michael,


Well if it's not functioning as expected with re-timing then there must be some issues with your code, or you missed some steps during migration. Are you sure you're using the correct compiler settings? Have you set the same Verilog/VHDL version as in Vivado? What steps did you take when you migrated from Vivado to Quartus?


Regards.

Nurina


Nurina
Employee
254 Views

Hi Michael, do you have any updates?


Nurina
Employee
210 Views

Hi,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!

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