Here is the device I use:1SG280LN2F43I2LG
There are several phenomena：
1. if I choose the option of allow retiming register, the data output will be wrong or no data ,with good timing closure. however, I don't choose the option, data output is right ,with bad timing closure.
2. I use the dont_retime attributes for part of modules , the result may be right or wrong at different frequencies .
I need your help with my problem , thank you.
If you're meeting timing, but not getting the outputs you expect, then chances are your design code is not doing what you intend. Perform a functional simulation or use a hardware debug tool like Signal Tap to verify the design in hardware.
Thanks for your answer.
You should scan the record above, my problem is that as long as this setting is turned on, the data output is wrong .And I have tested my code in xilinx vu9p with no wrong .Because this project is big, so hardware debugging will take me a lot of time.
Can your team help give some suggestions？tks.
Well if it's not functioning as expected with re-timing then there must be some issues with your code, or you missed some steps during migration. Are you sure you're using the correct compiler settings? Have you set the same Verilog/VHDL version as in Vivado? What steps did you take when you migrated from Vivado to Quartus?
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