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Why do I get the following relsult in my FIR filter output




I want to simulate my FIR filter in Verilog. But I get the wrong result. For example, when simulating a complete sinusoidal wave as input, I get the following result:




Here is my code in Verilog:


`timescale 1ms / 1ps

// Module Name: FIR_Filter

module FIR_Filter(clk, reset, my_data_in, my_data_out);

parameter N = 8;

input clk, reset;
input signed [N-1:0] my_data_in;
output reg signed [N-1:0] my_data_out; 

// coefficients defination
// Moving Average Filter, 3rd order

//wire [7:0] b0 = 8'b0_0001010; 
//wire [7:0] b1 = 8'b0_0010000; 
//wire [7:0] b2 = 8'b0_0101000; 
//wire [7:0] b3 = 8'b0_1000000;
//wire [7:0] b4 = 8'b0_0101000; 
//wire [7:0] b5 = 8'b0_0010000; 
//wire [7:0] b6 = 8'b0_0001010; 

wire signed [N-1:0] x1, x2, x3, x4, x5, x6; 

// Create delays i.e x[n-1], x[n-2], .. x[n-N]
// Instantiate D Flip Flops
DFF DFF0(clk, reset, my_data_in, x1); // x[n-1]
DFF DFF1(clk, reset, x1, x2);      // x[x[n-2]]
DFF DFF2(clk, reset, x2, x3);      // x[n-3] 
DFF DFF3(clk, reset, x3, x4);      
DFF DFF4(clk, reset, x4, x5);
DFF DFF5(clk, reset, x5, x6);

//  Multitiplication
wire signed [N-1:0] Multi0, Multi1, Multi2, Multi3, Multi4, Multi5, Multi6;  
assign Multi0 = (my_data_in>>4)+(my_data_in>>6); 
assign Multi1 = (my_data_in>>3);  
assign Multi2 = (my_data_in>>4)+(my_data_in>>2);  
assign Multi3 = (my_data_in>>1);  
assign Multi4 = (my_data_in>>4)+(my_data_in>>2);
assign Multi5 = (my_data_in>>3);  
assign Multi6 = (my_data_in>>4)+(my_data_in>>6);  

//assign Multi0 = my_data_in * b0;
//assign Multi1 = x1 * b1;
//assign Multi2 = x2 * b2;
//assign Multi3 = x3 * b3;
//assign Multi4 = x4 * b4;
//assign Multi5 = x5 * b5;
///assign Multi6 = x6 * b6;

// Addition operation
wire signed [N-1:0] Add_final_value; 
assign Add_final_value = Multi0 + Multi1 + Multi2 + Multi3 + Multi4 + Multi5 + Multi6; 

// Final calculation to output 
always@(posedge clk)
my_data_out <= Add_final_value; 


module DFF(clk, reset, my_data_in, data_delayed);
parameter N = 8;
input clk, reset;
input [N-1:0] my_data_in;
output reg [N-1:0] data_delayed; 

always@(posedge clk)
    if (reset)
    data_delayed <= 0;
    data_delayed <= my_data_in; 




Input data is in 2's complement format, between -64 and 63. So, despite the fact that FIR filter coefficients' sum is larger than one, we are sure that the output won't overflow. but as you can see in the image, overflow has been occurred in our output. I do not know what the reason is. one important point to note is that our output is always positive. 





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1 Solution
Valued Contributor III
You are using logical right shift for signed variables which corrupts the sign bit. Try arithmetic shift.

View solution in original post

5 Replies
Valued Contributor III
You are using logical right shift for signed variables which corrupts the sign bit. Try arithmetic shift.

Thank you! excellent answer. After doing some minor changes to my design (especially those which you've mentioned), my ideal simulation in modelsim worked great. However, after synthesizing my project using design vision, I could not get appropriate results (I mean in non-ideal simulation using the files which were produced by design vision). it gives a lot of &hold and &setup time error and output is completely don't care. I have checked the schematic view in synthesizer. It seems flawless. just in the log file, synthesizer said:


Warning: Verilog writer has added 4 nets to module FIR filter using SYNOPSYS_UNCONNECTED_ as prefix. Please use the change_names command to make the correct changes before invoking the Verilog writer. (VO-11)


Can you help me?

Thank you

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When I click on check design in synopsis, the following warnnings come up:


Warning: In design 'FIR_Filter_DW01_add_0', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter_DW01_add_0', port 'CO' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter_DW01_add_1', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter_DW01_add_1', port 'CO' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter_DW01_add_2', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter_DW01_add_2', port 'CO' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter', the same net is connected to more than one pin on submodule 'add_2_root_add_0_root_add_59_6'. (LINT-33)
Net 'add_6_root_add_59_6/carry[6]' is connected to pins 'A[7]', 'A[6]''.


Do these warnings cause error in modelsim?

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Please refer to below explanation.

For LINT-28 (warning) In design.


This warning alerts you that a port in a design is not connected to any nets. This usually indicates

that a design has not been correctly specified. However, there are some situations where, as a

designer, you choose to specify a port on a design for compatibility reasons, even though the port

is not internal to design use. The Synopsys tools leave unconnected ports alone, with one

exception; that is, you specified that a given input port is opposite or equal to another input port in

a design.


Make sure that you want the named port to exist in the given design, even though it has no

nets connected. Remove the port from your design if you choose.

For LINT-33 (warning) In design.


check design issues this warning when it finds an instance of a hierarchical design (for

example, a sub-module) that has more than one input connected to the same net. This

warning is issued to verify that these are desired connections on the submodule. Be aware that

compile can remove logic in a design that is redundant. So, compile can produce designs that

display this warning if it determines that multiple inputs on a submodule are driven by the same

logical signal.


Verify that you want the given submodule inputs connected to the same logical signal. If you have

run compile, you might want to use verify to verify the optimized design with your original. Or, use

the -verify option to compile whenever feasible.

Thank you

Kshitij Goel

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As we do not receive any response from you on the previous answer that we have provided. Please login to ‘’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you

Kshitij Goel

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