Will the 5CEFA4U19 chip work without some power pins connected as suggested by the Quartus migration feature.

[SWilb1]

I am designing a Cyclone V E (U19-484 pins) board to have vertical migration from A4 to A9. I used the migration feature in Quartus with 5CEFA4U19 as the target and the A5, A7 and A9 chips selected to be compatible. The compiled project produced a pin map. Unfortunately some of the power pins in the A4 chip are marked as NC in the A9 chip pin connection documentation. The migration pin map from Quartus says no connection for these power pins. Specific pins are: D4, E1, J1, J2, R1, R2 and Y4. Will the A4 device really work without these power pins connected, or are these devices really not vertically migrateable as claimed in other documentation?

[a_x_h_75]

No firm answer in here I'm afraid. I saw you post this previously, thought it sounded wrong and assumed you weren't doing something correctly. So I did some tests and concluded exactly the same as you.

I have successfully used device migration previously, both with Cyclone IV and V (not that package), without issue. I'm pretty sure I'd have checked the power pins, as you have. I assume (I cannot recall) that I didn't find any inconsistencies.

There are plenty of devices (Intel and beyond) that share power pins internally such that both A4 & A9 would work correctly. However, I'm not in a position to confirm this either way for this device.

I suggest you raise a ticket via MyIntel

https://www.intel.com/content/www/us/en/my-intel/sign-in.html

Cheers,

Alex

[MBenca]

Hi,

I would recommend to look to Cyclone V Device Family Pin Connection Guidelines (https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/cyclone-v/pcg-01014.pdf)

There is the following fragment as an explanation of NC pin, section Pin Connection Guidelines, Reference Pins, p.17:

Cyclone V Pin Name = NC, Pin Type = No Connect, Pin Description = Do not drive signals into these pins. Connection Guidelines = When designing for device migration, these pins may be connected to power, GND, or a signal trace depending on the pin assignment of the devices selected for migration. However, if device migration is not a concern, leave these pins floating.

Maybe I am wrong but this fragment sounds to me in case of a device migration it is possible to connect NC pins to active signals such as GND or power.

Regards,

Martin

[SWilb1]

Thank you. I was aware of the pin connection guidelines you quote. However, the issue really is, the Quartus vertical migration feature says to leave unconnected all the noted pins (and a few others), including the relevant power pins in the A4 device. This is in direct conflict with this section of the guidelines. I guess my more accurate question is, will it harm the A5-A9 chip to connect power to pins marked as NC in order to power the A4 chip, which I am certain will not work correctly without connecting all its power pins. As I see it there are only three possibilities: 1) connect power to the pins marked NC in the larger chips but are power pins in the A4 device, following the guidelines; 2) do not connect these pins according to the Quartus vertical migration results (then the A4 device will not work but the others will); 3) vertical migration capability of the Cyclone VE U19 package does not really cover A2 through A9 as stated in the device overview and elsewhere.

Of course I prefer possibility 1 to be correct allowing full migration between A4-A9, but I don't want to risk the substantial cost of assuming this to be true and finding out later it is not.

[SWilb1]

Can anyone confirm by certain knowledge that pins marked "NC" in the pin connection guidelines for Cyclone V are truly not connected to the die? If NC does mean "not connected to the die," then it will be perfectly safe to apply power to those pins when the particular device being migrated to calls for a power connection. This is a simpler question to answer, and someone at Intel (or elsewhere) will really know that answer. Still doesn't account for the discrepancy between Quartus migration tool and the more and more likely eventuality that power may be tied to otherwise NC pins within the migration family. This would seem to be an error in the Quartus migration feature. Hopefully we can finally put this to bed for all those who have been confused by this important detail of vertical migration.

[SreekumarR_G_Intel]

The NC (No-Connect) pins are not physically connected to the die, so you can safely connect these pins to power or GND as per the larger device that you are migrating to, without causing any damage.

Thank you,

Regards,

Sree

[SWilb1]

Thank you for the confirmation. Oddly it is the smaller die that has the extra power connections. Now the remaining issue is the bug in Quartus vertical migration tool, which does not correctly show the power connections for proper migration. Now I have to manually compare the spread sheets for each one of the chips in the desired migration path. Each pin that is supposed to be power, but is NC in another chip in the family must be properly identified and connected. At least users should be warned not to assume the migration tool is giving correct or complete results.

[SreekumarR_G_Intel]

I agree with you , I also faced the similar situation and i raised t internally for the same ..Let see the future release of quartus.

Thank you for letting us know the issues.

Regards,

Sree