I'm trying to use the Avalon Verification Suite to verify an IP component with Avalon Streaming interface. The IP is the University Program Video Edge Detection, and I have slotted it in between an Avalon-ST Source BFM and an Avalon-ST Sink BFM. (see attached zip file for the Quartus/SOPC project file).
I am having some difficulties writing the testbench in SystemVerilog to be executed in ModelSim. The IP accepts a stream of 8-bit unsigned integers which I can implement by reading data from a file. But then I don't know how to make the BFM read in the stimulus and also read out the output. I've tried looking at some example tutorial files to write a testbench (see attachment sopc_system_tb.v), but I have not been successful. I am not too sure how to give values to startofpacket and endofpacket either. In my code, I am reading in packets of 4 bytes, but I don't know if this step is any good. Also, if I simulate the code in ModelSim, I get a timeout error message saying FAILURE: sopc_system_tb.dut.the_st_source_bfm.st_source_bfm : Response Timeout. Could you please look at my current SystemVerilog file (file has been renamed to .v so that I can attach it to this message) and guide me through writing this BFM ST testbench? Thanks