Writing to HPS memory from FPGA

[kalamitas]

Hello everyone,

I'm trying to build a system based on the CycloneV to make use of the FPGA for some calculations and use the results on the HPS.

So far I'm pretty sure I have figured out transfering data to the FPGA via some OCR based on https://github.com/robertofem/CycloneVSoC-examples (at least the example works, if it actually works with getting data from the OCR into my module remains to be seen).

I wanted to write my output as 128bit bundles via the F2H-bridge to the memory of the HPS, mastering the write from the FPGA side. For that I have connected an Avalon Memory Mapped Master in my component to the f2h-slave in the HPS via the Platform Designer. From my understanding I should be able to access the data on the HPS by mapping the memory starting with 0xC0000000 as a base (the HPS2FPGA bridge base address) and adding an offset. On the FPGA side I'm writing to the address at 0xC0000000+offset. I should be able to now see the data on the HPS, shouldn't I? If I read the contents of the address right now I only get scrambled data instead of the bit pattern I wrote.

I would prefer to not write the output to FPGA OCR and then read that via the DMA mastered by the HPS to reduce needed synchronization between the HPS and FPGA (and because memory is precious).

I looked at the example on this side for the FPGA-to-HPS-bridge-design but that writes directly to the sdram via the FPGA-SDRAM bridge (with all the coherency issues). Is the example the only way or would my design work?

On that note, is there a good way to read data directly from the HPS RAM via the FPGA without using the first example without too much latency? In the end my design should be able to transfer about 2MB of data in less than 50ms from HPS to FPGA and about 1MB of data from FPGA to HPS in about the same timeframe.

Thank you for your time in advance!

[JingyangTeh]

Hi Kalimitas

Thank you for reaching out to us.

I am Jingyang and will be attending to this case.

Please give me some more time to seek more advise from my colleague.

Regards

Jingyang, Teh

[JingyangTeh]

Hi Kalimitas

After consulting a colleague , the example is able to work.

The HPS could read the values from OCR directly but you would need to make sure the data a sync between the FPGA and HPS before any side read or write the values.

There is this IP called cache coherency translator that could be used to accessed the OCR and it will maintain the coherency between both sides.

Unfortunately the IP is not available for Cyclone V.

However you could read the OCR through the Accelerated Coherency Port for Cyclone V

There is no reference design for accessing the ACP, but you could refer to the document below on the signals required and its description.

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/accelerator-coherency-port.html

Regards

Jingyang, Teh

One way is to

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Any update on this case?

Regards

JIngyang, Teh

[kalamitas1]

I've decided to use the linked github example by using a driver for the DMA in the HPS to manage the data transfer.

Data transfers are working, reading data into my module is not. I'm not quite sure what the problem is, it seems the read request via the MM master to the slave input of the on-chip RAM is stalling. From what I understand, if I configure my master to use symbols for addressing I'm counting in bytes. So if I want to read a 128 bit word I assert read and the needed address, wait until the waitrequest signal goes low to deassert my read and then wait for readdatavalid to be asserted. If I want to access the next word I would increment the address by 16 (for the 16 bytes I just read) and do the whole thing again. But I'm either not getting the readdatavalid or waitrequest is constantly asserted. Or my addressing is wrong (I use the address range as given in Platform Designer) and I need to increment the address by only 1 to access the next word?

I'm the original poster, when I tried to log in again it requested me to choose another displayname...

[JingyangTeh]

HI Kalimatas

Do you share me a screenshot of the signals that you are seeing?

And also a screenshot of your platform designer connections and settings.

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Any update on this case?

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Regards

Jingyang, Teh