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ChanceG
Beginner
95 Views

XCVR_ANALOG_SETTINGS_PROTOCOL XAUI

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Hello-

I have unsuccessful trying to find out exactly what analog settings the Subject QSF setting enables (the RX side in particular).  Is that in the fitter report?  If so, I found a section that has:

 

-- Receiver Buffer:
-- Receiver Buffer Location; HSSIPMARXBUF_X185_Y51_N36:
-- DC Gain: 1
-- AC Gain: 1
-- Termination: 100 Ohms
-- Equalization Bandwidth Selection: bw_half_6p5
-- Serial Loopback: lpbkp_dis
-- VCCELA Supply Voltage: vccela_1p0v

 

Is that the actual settings?  If so, does anyone know what an equalization bandwidth of "bw_half_6p5" is?  I don't see anything about DFE.  I assume it's not enabled?

Thanks!

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1 Solution
CheePin_C_Intel
Employee
63 Views

Hi,


Regarding to your inquiry on the DFE, as I understand it from the V-Series Transceiver PHY IP Core User Guide, the SV DFE is configured through registers in user mode but not QSF assignment. This could explain why you are not seeing DFE related parameters in the Fitter report. You may refer to "Transceiver Reconfiguration Controller DFE Registers" in the user guide for further details on how to configure the DFE registers. 


Please let me know if there is any concern. Thank you.



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7 Replies
CheePin_C_Intel
Employee
83 Views

Hi,


As I understand it, you have some inquiries related to checking the PMA analog settings from the Fitter report. Yes, your understanding is correct. You can find out the settings from Fitter report. The section that you are showing seems to be valid section with the right information. Note that some of the information might be referring to internal settings apart from those described in the user guide.


Regarding your inquiry on the bw_half_6p5, just would like to check with you which specific device that you are using so that I could further check if it is an internal setting.


Please let me know if there is any concern. Thank you.



ChanceG
Beginner
78 Views

Hello-

Thanks for that.  The specific part is 5SGXMA3H3F35C2N

Thanks!

CheePin_C_Intel
Employee
63 Views


Hi,


Thanks for your update. For your information, as I search into the SV handbook and XCVR PHY user guide, I am unable to locate any specific info on the "Equalization Bandwidth Selection". I believe this is an internal setting auto-configured by Fitter.


Please let me know if there is any concern. Thank you.


CheePin_C_Intel
Employee
63 Views

Hi,


Regarding to your inquiry on the DFE, as I undrestand it from the V-Series Transceiver PHY IP Core User

Guide, the SV DFE is configured through registers in user mode but not QSF assignment. This could explain why you are not seeing DFE related parameters in the Fitter report. You may refer to "Transceiver Reconfiguration Controller DFE Registers" in the user guide for further details on how to configure the DFE registers. 


Please let me know if there is any concern. Thank you.



CheePin_C_Intel
Employee
64 Views

Hi,


Regarding to your inquiry on the DFE, as I understand it from the V-Series Transceiver PHY IP Core User Guide, the SV DFE is configured through registers in user mode but not QSF assignment. This could explain why you are not seeing DFE related parameters in the Fitter report. You may refer to "Transceiver Reconfiguration Controller DFE Registers" in the user guide for further details on how to configure the DFE registers. 


Please let me know if there is any concern. Thank you.



View solution in original post

ChanceG
Beginner
54 Views

Thank you!

CheePin_C_Intel
Employee
24 Views

Hi,


You are welcome. I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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