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Altera_Forum
Honored Contributor I
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ZDB Mode - How to verify correct routing / resource usage

Hi all, 

 

how can I verify that my output clocks are routed directly from the PLL to the clock output pin and not through logic or clock networks? I want to make sure that I'm using zero-delay buffer mode correctly. 

 

Many thanks in advance! 

 

Regards, sö
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