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Zero-delay PLL dividing frequency by 2

Honored Contributor II


I come today with a new problem which I'm hoping is just something silly I'm not seeing and configuring incorrectly. 


I've created a new project for a Cyclone V FPGA, instantiated a zero-delay fractional PLL (it was an integer previously but the compiler notified me it is done with a fractional one either way so I just went ahead and changed it) and connected it's input to a clock control block. The clock control is needed because the clock I'm using to test this cannot reach the fPLL given the output clock I've assigned, this shouldn't be a problem though because it's just for testing purposes, the final design will have the correct dedicated input/output clocks. 


The zero-delay PLL has 2 output connections needed: 

1) The output pin to compensate for zdbfbclk (actually a bidir connection) 

2) A regular output clock 

The first one goes to the dedicated output clock I wish to compensate and the second one to another (not dedicated clock pin) output. Jitter and such is not important on the latter since I just wanted to check if everything was working. 


The input clock is 125 MHz, I've configured the PLL for 125M input and the only output clock for 125M as well. 


Now for the actual problem... if I simulate this everything works as expected: the PLL locks after a couple of clock cycles and then I have both output clocks from the PLL at 125M. I'm not simulating the clock control block though because I can't get Modelsim to actually work with it, I believe this shouldn't be a problem because it really does nothing more than route the input clock to another inner clock, so I just replace the block with an assignment when simulating. 


When I then go ahead and download this to my FPGA, the compensated output clock turns out to be at 62.5M (half of the intended 125M) while the output clock on the generic pin is at the correct 125M frequency. 

Is there some kind of configuration I'm missing?? 


Looking at the post-fitting map viewer everything seems fine. The input clock goes through the clock control block into the fPLL. The fPLL's ZDB port connects to the PADOUT of a bidir cell and the cell's PADIN connects to the FBCLK and CORECLKFB ports of the fPLL. 


Is this the intended functionality of the zero-delay PLL? 


I'd appreciate anyone pointing me in the right direction! 


Thanks!! =)
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