a few questions about using Virtual JTAG ip core

[RobertLiang]

Dear experts,

I've met a problem when I was researching that how to use a virtual JTAG core to transfer data between a PC and the board. I've read Virtual JTAG Intel FPGA IP Core user guide ，but there's something I didn't figure out:

1. Is there any detailed description of the virtual state machine? I learned to use some one-hot decoding like 'virtual_state_sdr' to tell my logic to get data from "TDI", but there isn't a concrete guide to tell me how to take advantage of all these state-machine signals.

2. In the example code below (excerpted from page 27)，I know the "bypass_reg" is meant to let 'tdo' have some "value" when the 'vir' is selecting another virtual DR chain.  But I don't totally understand why I should write code like the example( and 'bypass_reg <= tdi' is a syntax error) . Is there any timing diagram to illustrate how to execute a read or write transaction? I can't find this support.

// Bypass used to maintain the scan chain continuity for
// tdi and tdo ports
bypass_reg <= tdi;
// Data Register Block
always @ (posedge tck)
  if ( load && sdr )
    tmp_reg <= {tdi, tmp_reg[3:1]};
// tdo Logic Block
always @ (tmp_reg[0] or bypass_reg)
  if(load)
    tdo <= tmp_reg[0];
  else
    tdo <= bypass_reg;
endmodule

3. I can roughly know how to use 'sdr' 'e1dr' to perform a write transaction to the board, but there isn't an example to show how to read data from the board.

If there's any document for reference that can solve my questions, I will be very happy!

Thank you!

[RobertLiang · Accepted solution]

Hello, 

I have already solved this problem, and I'd like to share my experience with others.

1. No, the document of "virtual JTAG" is not that clear, but basically, we can use v_sdr to shift data both in read or write transaction; use v_cdr to indicate that parallel data which is to be transmitted to a PC should be prepared ready; use v_udr to read the shift register to get the parallel data output. Other states are not important.

2. If there's a read transaction (transmit data from FPGA to PC), shift data to 'tdo' when v_sdr high. If not, connect 'tdo' directly with 'tdi'.

3. The document can't help to provide more examples, write a test project is a better way to understand the usage of this core.

[YuanLi_S_Intel]

Thank for your sharing. I am sure other people will be benefited as well.

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.