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I am planing to use altremote_update mega function to update remotely .Currently I am doing some tests on this mega function .
What I am trying to do is to have 2 SOFs .1 for factory image and the other for application image . I combined these 2 SOFs (SOF image0 start from 0x0 while image1 start from 0x200000 ) in one jic file ,and write it to EPCS64 successfully . When FPGA re-poweron ,it can load the factory image automatically and succesffully ,then I set some parameters in the altremote_update mega function (the most important param is boot_address =0x80000 ,because the UG of altremote noticed 22bit input connect to the upper 24bits of address ) and trigger the mega function ,then FPGA became a stone, even cannot come back to factory image .... :( I measured the pin of the stone ,found that nconfig is high ,nstatus is high while conf_done is low .Then I use siganltap download the factory sof into FPGA ,read some information from the mega function about the error bit ,it is 0x10 ,that means "external nCONFIG assertion" .But something strange is pin nCONFIG is connected to VCC(3.3V) via a 10K resistor . Could anyone kindly help me with this problem ,or kindly tell me how to debug the stone ?I have no idea on how to dig out more useful information .Link Copied
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Hello all,
Problems above has been solved ,root cause is my partner put the wrong resistor between VCC and pin nSTATUS .The actual resistor is not 10K ohm but 10 ohm .So nstatus is always high ,and FPGA is just waiting for the negedge of nSTATUS . Just share it with all of you ,hope that would help more or less . BTW , I found this forum really helpful to me ,I've leant a lot here.
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