Dear:
I'm using stratixGX EP1SGX10CF627 chip, in my design, one altgxb is used, and its output of coreclk_out (should be 80MHz, because input data rate is 800M) is used as input of another pll (rxpll, input clock should be 80MHz).
When I complie the project, there is critical warning hint that coreclk_out is 120MHz, not 80MHz as designed:
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Critical Warning: Input port inclk[0] of PLL "rxTxPll:rxTxPll_1|altpll:altpll_component|pll" and its source clk[2] (the output port of PLL "starLinkSlave:starLinkSlave_1|stratixGx4TransceiverShell:stratixGx4TransceiverShell_1|stratixGx4Transceiver:stratixGx4Transceiver_1|altgxb:altgxb_component|pll[0]") have different specified frequencies, 80.0 MHz and 120.0 MHz respectively
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the code is as attached.
Please help to find what's the reason, as I understand, input data rate is 800M, tx coreclk_out should be 80MHz, is it?
Thanks in advance.
