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Altera_Forum
Honored Contributor I
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altlvds_rx with offset input clock

I'm trying to get the altlvds_rx block to work with this TI input for their sn65dsi84. They start to transition the first bit of serial data 90 degrees from the rising edge of the LVDS clock. So far I can't configure my block correctly so that this works in simulation. I always seem to get the wrong output data on rx_out. I assumed maybe I could set the inclock_data_alignment to 90_DEGREES but I got the same wrong data. I thought that was odd too, I would have expected that to at least make a change. Any idea what I'm missing here? 

 

For example for one LVDS clock cycle I'll drive 0101 on the four lvds inputs but I'll get 000000 1111111 0000000 11111110 instead (6 zeros 7 ones 7 zeros 7 ones 1 zero). It's like I'm off by a cycle. If I hold the same data for multiple cycles the pattern comes as expected later on. So I can only assume I'm missing a key parameter here.
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