Hi,
I'm looking for a way to implement a configurable DDR memory controller in VHDL on Cyclone III. AFAIK I need to use altmemphy, but top level for this function doesn't support configuration (using packages or generic parameters). Lower levels are written in Verilog, and I see they support some form of configuration using parameters. Is there any documentation available for altmemphy configuration? I would also appreciate any docs regarding use of altmemphy (the only thing I found in documentation was advice to run memory controller simulation and reverse engineer use of all signals). Thanks in advance.
