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Altera_Forum
Honored Contributor I
784 Views

banks sharing VCCPD pins

I am working on a Cyclone V project: part 5CSEBA5U23C8SN 

 

In addition to the HPS "ARM" core I am also creating a NIOS system with its own DRAM, DDR3L, 32 bits wide 

 

I decided to put the DRAM signals on bank 4A. One reason was to facilitate board routing, but the other was because it appeared to be the bank that fit best, getting all the DRAM signals in with minimal left overs. This was imortant as the IO voltage on the bank will need to be 1.35 V and there is no other logic on the board that would interface at this voltage level. 

 

I thought it was a good solution until I discovered that the VCCPD pins are shared between banks 3B and 4A (VCCPD3B4A) 

 

There are 6 of these pins, why couldn't banks 3B and 4A be independent? 

 

Anyway, now I am having difficulty getting enough 3.3V I/O for the other functions due to the limitations of the VCCPD 

 

So I want to make sure I understand this properly. 

 

With any VCCIO voltage 2.5 or less, VDDPD must be 2.5 Volts. Is that correct? 

 

Now comes the really confusing part: With a VDDPD of 2.5 volts, it appears that I can't have a 3.3V LVTTL output, but I can have a 3.3V LVTTL input. 

Is that right? 

 

Is there any reason that I wouldn't want to have a 3.3 V signal as an input on bank 3B when VCCPD3b4A is 2.5 Volts? 

 

 

Thanks 

 

Rod
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Altera_Forum
Honored Contributor I
42 Views

Your understanding is correct - on both fronts. 

 

I recommend, if you haven't already, running your project through Quartus and using the Pin Planner to try anything you're questioning. If you inadvertently put a 3.3V output into a bank powered at 2.5V, Quartus will reject it. However, it'll happily accept a 3.3V input into the same bank. Once through Quartus you can examine the .fit.rpt report file. The 'All Package Pins' table will tell you how Quartus is expecting every pin to be connected. 

 

Cheers, 

Alex
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