Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

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Stratix V board power cycled during fpga programming -->no longer possible to program

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I instantiaze a pll with 4 output clock,but when I use Derive PLL Clocks command in Timing Analyzer, it only derive two generated clock?

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Arria 10 SERDES with Global Clock

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how about to generate a reset using a counter enabled by the locked signal of the pll ?

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how to instantiate the Altera v17.0 pll in the verilog file.can i get the instantiation code.

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804

Intel DH67VR BIOS problem

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1106

While running the cyclone V ,the following routing problems are showing

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Can a Cyclone IV Low Voltage (1V core) be dropped in to an 1.2V socket

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1056

jtagd JTAG chain broken on Ubuntu 19.04 only on logical cable 1

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2964

I do not have the input reset signal from the outside of the Altera FPGA,and want to generate reset internally;can I do like below ?

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866

I have instantiate two BRAM with M9K,why the percent of usage of Embedded Multiplier 9-bit elements is zero ?

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736

How to prepare a rpd file

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2853

downloading .jic into IS128LP128 (8-pins) and connection between CycloneV and IS128LP128 (8-pins).

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4 Replies 715 Views

715

Question regarding MAX10 and clock switchover

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1327

What are reference clock frequencies supported by dedicated xcvr reference clock pins of Stratix 10?

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1287

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Programmable Devices

Discussions

Stratix V board power cycled during fpga programming -->no longer possible to program

I instantiaze a pll with 4 output clock,but when I use Derive PLL Clocks command in Timing Analyzer, it only derive two generated clock?

Arria 10 SERDES with Global Clock

how about to generate a reset using a counter enabled by the locked signal of the pll ?

how to instantiate the Altera v17.0 pll in the verilog file.can i get the instantiation code.

Intel DH67VR BIOS problem

While running the cyclone V ,the following routing problems are showing

Can a Cyclone IV Low Voltage (1V core) be dropped in to an 1.2V socket

jtagd JTAG chain broken on Ubuntu 19.04 only on logical cable 1

I do not have the input reset signal from the outside of the Altera FPGA,and want to generate reset internally;can I do like below ?

I have instantiate two BRAM with M9K,why the percent of usage of Embedded Multiplier 9-bit elements is zero ?

How to prepare a rpd file

downloading .jic into IS128LP128 (8-pins) and connection between CycloneV and IS128LP128 (8-pins).

Question regarding MAX10 and clock switchover

What are reference clock frequencies supported by dedicated xcvr reference clock pins of Stratix 10?

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Cyclone V issue with Fractional PLL and Reconfig IP Modules

I350 igb driver failed with error -2

Request for the Product Lifecycle Status

Re: USB Blaster selection criteria

Solution: USB Blaster Driver for Windows 11 ARM