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Novice
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bug of SPI ss_n?

Software version:Quartus Prime Lite Edition 18.1

 

I would like to let DE0-Nano be a SPI Master to control 3 SPI slave.

I add SPI IP and set ss_n as 3.

After generating verilog file, there is only one xx_external_SS_n in xxx_inst.v for user.

Is it a bug?

 

SPI_IP_setting.png

spi_inst.png

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Employee
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Hi!


First of all, thanks for reaching us,


regarding your question, the reason why it seems to be just one xx_external_SS_n in the *_inst.v file it's because appears as an array, not as individual connections.

if you navigate to Soc_system -> synthesis ->submodule_spi.v you'll find that its declared as 'output wire [2:0] spi_o_external_ss_n'.


Please let me know any questions you may have.


Regards,

-Eliath Guzman


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