bypass the need for dedicated clock pins

[Altera_Forum]

Hi,  

i am doing a project at the university and the card that my fpga would be on is already printed (The FPGA is EP2S130). I need to get data from SERDES on another card (in LVDS), and because I cant use DPA (the ONLY pins that i can use are from BANK 6 which doesn't have DPA capability), I need to get the tx_outclock of the other SERDES along with the data.  Now, the problem is that there arent any clock dedicated pins among the pins that i can use. Therefore I need to know if i can get the rx_clock (the othersides tx_clock) in normal LVDS pins and tell Quartus to ignore it.  When i just connect the incoming clock to normal LVDS pins it generates error that the pll that gets the clock is driving the RX_SERDES and therefore it must get the clock from COMPENSATED pins.     Please help me, My grade really depends on it :-). Thanks ahead, Itayyeka.

[Altera_Forum]

For low and medium speed, deserialization can work in LEs. Hardware SERDES won't be usually without an input clock supplied through dedicated clock inputs and fast PLLs.

[Altera_Forum]

first of all, thank you for answering. 

I didnt quite understand, is there a way to tell QUARTUS to ignore this problem if i can assure that the data rate would be slow or medium speed? And I am not really familiar with the term "LEs", what does it mean?  again, thanks ahead.

[Altera_Forum]

Logic elements.

[Altera_Forum]

--- Quote Start ---  I didnt quite understand, is there a way to tell QUARTUS to ignore this problem if i can assure that the data rate would be slow or medium speed?  --- Quote End ---   The problem is, that the Stratix II devices (as far as I'm aware of), don't have a clock path available to feed the clock input of a dedicated SERDES blocks from a regular IO pin. So you can't use the SERDES hardware.

[Altera_Forum]

thank you, those are bad news but thank you very much:-)

[Altera_Forum]

The other problem is, that PLL clock processing isn't available for clock from I/O pins. This means, that you need to supply the LVDS fast clock (1/2 data rate) from the transmitter side. Frame synchronization must use an additional signal or sync pattern embedded in the data stream.