cache memory for reading and writing

[Altera_Forum]

Hi all 

 I am using a memory of 16 8-bit words that is preloaded with specific operands. My memory module has 5 ports which are "dcenbl" to enable the cache for read or write operation, "rdwr" to allow reading (rdwr=1) or writing (rdwr=0), "dcaddr[3:0]" which selects an address in the cache to either read or write data, "dcdatain[7:0]" provides data for a write operation, and "dcdataout[7:0]" provides cache contents for read operation.  When I compiled my code, it is giving me an error showing that 'Cannot synthesize initialized RAM logic "dcache"' for the line reg [7:0] dcache [0:15] in the code.  Can anyone please tell me how to solve this error.  I am running my code in quartus 11.0 web edition using cyclone ii device.  ------------------------------------My code-----------------------------------   module mem_dcache (dcenbl, dcaddr, dcdatain, dcdataout, rdwr);  input [3:0] dcaddr; input [7:0] dcdatain; input dcenbl, rdwr;  output [7:0] dcdataout;  wire [3:0] dcaddr; wire [7:0] dcdatain; wire dcenbl, rdwr;  reg [7:0] dcdataout;  //define memory size:# of bits per reg;# of regs // 8bits per reg; 16 regs  reg [7:0] dcache [0:15];  //define memory contents initial begin  dcache [00] = 8'h00;  dcache [01] = 8'h22;  dcache [02] = 8'h44;  dcache [03] = 8'h66;  dcache [04] = 8'h88;  dcache [05] = 8'haa;  dcache [06] = 8'hcc;  dcache [07] = 8'hff;  dcache [08] = 8'h00;  dcache [09] = 8'h00;  dcache [10] = 8'h00;  dcache [11] = 8'h00;  dcache [12] = 8'h00;  dcache [13] = 8'h00;  dcache [14] = 8'h00;  dcache [15] = 8'h00; end  always @ (dcenbl or dcaddr or dcdatain or rdwr)  begin  if (rdwr==1) // if true, read op (ld regfile)  dcdataout = dcache [dcaddr];  else // if false, write op (st regfile)  dcache [dcaddr] = dcdatain; end endmodule

[Altera_Forum]

An initial statement is not synthesizable... it should be used in simulation only.  

Either you can instatiate Altera's RAM block or use a reset statement in your always block in which you can initialize the values.