can't read/write DDR2 with HPC II

[Altera_Forum]

Hi, 

 I try to read/write data to ddr2 using altmemphy HPC II in full data rate. I use Cyclone IV GX FPGA Development Kit Board, DDR2 modules are Micron MT47H16M16 with 16bits interface (32bits for local interface).  My code used to work (simulation and hardware) with DDR1. The HPCII seems to be the same for DDR2 so I use similar vhdl code to manage the local interface.  I do a simple test: write 4x32bit and then read it back. Both simulation and signal tap give the same result, read data are wrong. The simulation shows that dq/dqs signals are good during write sequence but the memory model isn’t fill out correctly so the read out fails.  I have checked "Chapter 8: Timing Diagrams 8–5/DDR and DDR2 High-Performance Controllers II" in external memory interface doc but I didn't found the problem. Controller or memory model problem ??  I attached the result of simulation which gives the same result as signal tap (for local interface).  Thanks for helping !

[Altera_Forum]

Hi SebastienG, 

 I would like to ask you if you could solve this problem. Also I wanted to ask if you had problems with the local_rdata bus. In my case I can't see any data in local_rdata bus during the functional simulation. However, using signaltap I can see the data in the local_rdata bus. I really need to see the simulation. I don't know if you have experienced this problem.  Thanks, Juan